IEEE Spectrum on MSN

Better hardware could turn zeros into AI heroes

Sparse computing enables leaner, faster AI ...
Semiconductor Engineering

Microarchitecture Tailored to 3D-Stacked Near-Memory Processing LLM Decoding (U. of Edinburg, Peking U., Cambridge et al.)

A new technical paper, “Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling ...

Apple set to overtake Dell as MacBook shipments rise against market decline

Market research firm Sigmaintell projects Apple will ship about 28 million MacBooks in 2026, up from roughly 23 million units ...
SDxCentral

Wind River to provide virtualization services to memory chip safety venture

Wind River is now part of the CHERI Alliance, the U.K. group aiming to enhance cybersecurity through hardware memory safety ...
Macworld

How Apple solved the RAM crisis before it even arrived

As RAM becomes more constrained and more important, Apple has crafted a system that does more with less—a lot more.
Electrek

Tesla announces HW4 Plus with doubled memory — will HW4 follow HW3 to the grave?

Tesla CEO Elon Musk revealed an AI4+ upgrade doubling RAM to 64GB — just hours after confirming HW3 can't do unsupervised FSD ...
Semiconductor Engineering

Research Bits: Apr. 21

Researchers at the University of California San Diego and Rutgers University created a brain-inspired device combining memory ...
IEEE

A Dual-Mode Online BISR Architecture for Interconnect and Memory Repair in Chiplet-Based Systems

Abstract: Chiplet-based systems provide a scalable platform for heterogeneous integration, but permanent faults in interconnects and memory cells challenge their reliability. While standards like ...
Communications of the ACMOpinion

The Golden Rule of Big Memory: Persistence Is Not Harmful

Large-scale applications, such as generative AI, recommendation systems, big data, and HPC systems, require large-capacity ...
Tech Xplore

CacheMind turns chip tuning into a conversation, exposing hidden cache failures and lifting processor performance

Researchers at North Carolina State University have developed a new AI-assisted tool that helps computer architects boost ...
IEEE

A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices

Abstract: This paper describes the architecture of the wafer-on-wafer (WOW) via-last through silicon via (TSV), named Bumpless Build Cube-TSV (BBCube-TSV). At first, the three types of TSVs, $\mu $ ...